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Accredited by NBA from 01.07.2016 to 30.06.2018

College CET Code: E013

Title      : Verilog-HDL
Subject      : Electronics and Communication
copyright © 2018   : PRASHANTH N
Author      : PRASHANTH N
Publisher      : Sai Vidya Institute of Technology
Chapters/Pages      : 6/227
Total Price      : Rs.      : 100
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Overview of Digital Design with Verilog HDL & Hierarchical Modeling Concepts Total views (0)  
Digital Circuit design has evolved rapidly over the last 25years.
Pages: 29
Price: Rs   
Basic Concepts & Modules and Ports Total views (0)  
A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation.
Pages: 42
Price: Rs   
Gate-Level Modeling & Dataflow Modeling Total views (0)  
Gate-level modeling is virtually the lowest-level of abstraction, because the switch-level abstraction is rarely used. In general, gate-level modelingis used for implementing lowest level modules in a design like, full-adder, multiplexers, etc.
Pages: 62
Price: Rs 0   
Behavioral Modeling Total views (0)  
Behavioral modeling is the highest level of abstraction in the Verilog HDL.
Pages: 45
Price: Rs 0   
Introduction to VHDL Total views (0)  
VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioral and structural style of modeling.
Pages: 35
Price: Rs 0   
Problems Total views (0)  
Pages: 14
Price: Rs 0   

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