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MDU Computer Architecture and Organization - Sem III
No Units Titles Sub Titles Chapters
1 Section A NA Boolean algebra and Logic gates, Combinational logic blocks(Adders, Multiplexers, Encoders, de-coder), Sequential logic blocks(Latches, Flip-Flops, Registers, Counters) Store program control concept, Flynn s classification of computers (SISD, MISD, MIMD) Multilevel viewpoint of a machine digital logic, micro architecture, ISA, operating systems, high level language structured organization CPU, caches, main memory, secondary memory units & I/O Performance metrics MIPS, MFLOPS VIEW CHAPTERS
2 Section B Instruction Set Architecture Boolean algebra and Logic gates, Combinational logic blocks(Adders, Multiplexers, Encoders, de-coder), Sequential logic blocks(Latches, Flip-Flops, Registers, Counters) Store program control concept, Flynn s classification of computers (SISD, MISD, MIMD) Multilevel viewpoint of a machine digital logic, micro architecture, ISA, operating systems,high level language structured organization CPU, caches, main memory, secondary memory units & I/O Performance metrics MIPS, MFLOPS VIEW CHAPTERS
3 Section C Basic non pipelined CPU Architecture and Memory Hierarchy & I/O Techniques CPU Architecture types (accumulator, register, stack, memory/ register) detailed data path of a typical register based CPU, Fetch-Decode-Execute cycle (typically 3 to 5 stage) microinstruction sequencing, implementation of control unit, Enhancing performance with pipelining The need for a memory hierarchy (Locality of reference principle, Memory hierarchy in practice Cache, main memory and secondary memory, Memory parameters access/ cycle time, cost per bit) Main memory (Semiconductor RAM & ROM organization, memory expansion, Static & dynamic memory types) Cache memory (Associative & direct mapped cache organizations VIEW CHAPTERS
4 Section D Introduction to Parallelism and Computer Organization [80x86] Goals of parallelism (Exploitation of concurrency, throughput enhancement) Amdahl s law Instruction level parallelism (pipelining, super scaling  basic features) Processor level parallelism (Multiprocessor systems overview) Instruction codes, computer register, computer instructions, timing and control, instruction cycle, type of instructions, memory reference, register reference I/O reference, Basics of Logic Design, accumulator logic, Control memory, address sequencing, micro-instruction formats, micro-program sequencer, Stack Organization, Instruction Formats, Types of interrupts; Memory Hierarchy VIEW CHAPTERS
 
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