Interline Publishing +91 98867 328 23 / 24 / 25   +91 80 2333 2824 Sign Up   Sign In
Interline Publishing
Skip to Reader

Procedure video

    Subscription offer
         (Unlimited Download)
Amount Validity
र 100 6 months
र 200 1 year
Search By
MDU Digital Electronics - Sem III
No Units Titles Sub Titles Chapters
1 Section A Digital system and binary numbers Signed binary numbers, binary codes, cyclic codes, error detecting and correcting codes, hamming codes Gate-level minimization The K-map method up to five variable, don t care conditions, POS simplification, NAND and NOR implementation, Quine Mc-Clusky method (Tabular method) VIEW CHAPTERS
2 Section B Combinational Logic Combinational circuits, analysis procedure, design procedure, binary Adder-subtractor, decimal adder, binary multiplier, magnitude comparator, decoders, encoders, multiplexers, demultiplexers VIEW CHAPTERS
3 Section C Synchronous Sequential logic Sequential circuits, storage elements latches, flip flops, analysis of clocked sequential circuits, state reduction and assignments, design procedure Registers and counters Shift registers, ripple counter, synchronous counter, other counters VIEW CHAPTERS
4 Section D Memory and programmable logic RAM, ROM, PLA, and PAL Design at the register transfer Level ASMs, design example, design with multiplexers Asynchronous sequential logic Analysis procedure, circuit with latches, design procedure, reduction of state and flow table, race Free State assignment, hazards VIEW CHAPTERS
About Us
Contact Us
Advertising Guidelines
Safe and Secure Payment
All major credit and debit cards are accepted.
Policies: Terms of Use | Privacy    Copyright © 2019 Interline Publishing. All rights reserved.