Interline Publishing
 info@interlinepublishing.com +91 98867 328 23 / 24 / 25   +91 80 2333 2824 Sign Up   Sign In
Interline Publishing
Skip to Reader

Procedure video
     
Home Authors Readers Search Claims Help Contact
Title      : CAD for VLSI
Subject      : VLSI
copyright © 2020   : Dr Niranjan N Chiplunkar
Author      : Dr Niranjan N Chiplunkar
Publisher      : NMAM Institute of Technology
Chapters/Pages      : 10/182
Total Price      : Rs.      : 91
 
 
To Purchase, select the individual chapter(s) or click "Select all" for the complete book.

Please scroll down to view chapter(s).

Hard copy available
Phone No:  9611266900
Email:  nchiplunkar@nitte.edu.in
Chapters
     
CONTENTS Total views (1)  
Overview of the basic VLSI Design, IC fabrication method, CMOS circuits, FPGAs and Technology mapping in FPGAs, Logic synthesis step of VLSI CAD, Boolean Algebra, Combinational and Sequential Optimization
Pages: 5
Price: Rs 0   
 
Basic VLSI Design Total views (0)  
The term VLSI refers to the ability to pack large number of gates/transistors on a small silicon area to achieve a given functionality.
Pages: 31
Price: Rs 15.5   
 
VLSI CAD Total views (0)  
VLSI CAD may be learnt in two different perspectives, one from the Layout Designers perspective and another from the CAD tool designer’s perspective.
Pages: 6
Price: Rs 3   
 
Partitioning in High level Synthesis Total views (0)  
The first step in high-level synthesis is compilation of the input behavior into an intermediate graph representation.
Pages: 22
Price: Rs 11   
 
Scheduling in High level Synthesis Total views (0)  
Scheduling algorithms partition the CDFG (discussed in earlier chapter) into subgraphs so that each subgraph is executed in one control step.
Pages: 25
Price: Rs 12.5   
 
Data Path Allocation in High level Synthesis Total views (0)  
Scheduling assigns operations to control steps and thus converts a behavioral description into a set of register transfers that can be described by a state table. The datapath is derived from the register transfers assigned to each control step; this task is called datapath synthesis or datapath allocation.
Pages: 16
Price: Rs 8   
 
Logic Synthesis Total views (0)  
Logic level synthesis determines gate level structure of a circuit. Each logic expression is converted to a logic circuit.
Pages: 27
Price: Rs 13.5   
 
Physical Synthesis Total views (0)  
Physical synthesis is a process of converting the circuit representation into a geometric representation.
Pages: 27
Price: Rs 13.5   
 
Appendix A: VHDL Basics Total views (0)  
VHDL (Very high speed integrated circuit Hardware Description Language) is a commonly used high level hardware description language.
Pages: 9
Price: Rs 4.5   
 
Appendix B: Graph theory Basics Total views (0)  
Most of the VLSI CAD tools use graph theoretic algorithms for their implementation. Hence a basic knowledge of graph theory is necessary to model and implement the VLSI CAD solution.
Pages: 14
Price: Rs 7   
 


 
Home
About Us
Payments
Contact Us
Claims
Help
Advertising Guidelines
Safe and Secure Payment
All major credit and debit cards are accepted.
Policies: Terms of Use | Privacy    Copyright © 2023 Interline Publishing. All rights reserved.